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   <div id="projectname">DM-CtrlH7-BF-DevProgram<span id="projectnumber">&#160;beta 0.1</span>
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   <div id="projectbrief">C.ONE Studio Damiao Development Board Framework</div>
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<div class="contents">
<div class="textblock">Here is a list of all documented variables with links to the class documentation for each member:</div>

<h3 class="doxsection"><a id="index_c" name="index_c"></a>- c -</h3><ul>
<li>C&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga86e2c5b891ecef1ab55b1edac0da79a6">APSR_Type</a>, <a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga40213a6b5620410cac83b0d89564609d">xPSR_Type</a></li>
<li>C1ICR&#160;:&#160;<a class="el" href="struct_h_s_e_m___type_def.html#adbebccb559027a2b858a3c85cc0b224a">HSEM_TypeDef</a></li>
<li>C1IER&#160;:&#160;<a class="el" href="struct_h_s_e_m___type_def.html#a69c1de4348244e1e36072b01bbcd0f75">HSEM_TypeDef</a></li>
<li>C1ISR&#160;:&#160;<a class="el" href="struct_h_s_e_m___type_def.html#a69174dfb50f2b0b06ed8ac999982f3b9">HSEM_TypeDef</a></li>
<li>C1MISR&#160;:&#160;<a class="el" href="struct_h_s_e_m___type_def.html#a93c90ca6f26ab1e3ae5d027761d41537">HSEM_TypeDef</a></li>
<li>CACR&#160;:&#160;<a class="el" href="struct_l_t_d_c___layer___type_def.html#af3708f47198ca52e0149584a8c382362">LTDC_Layer_TypeDef</a>, <a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga51f9bd107a4e1d46ba647384e5c825b5">SCB_Type</a></li>
<li>CALFACT2_RES14&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#ae2a9ddff6ae4c52a011f8f5fa15d8b57">ADC_TypeDef</a></li>
<li>CALFACT_RES13&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#acb8f02ad1b8f9e65955fc11f47ef2e4b">ADC_TypeDef</a></li>
<li>CALIB&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gafcadb0c6d35b21cdc0018658a13942de">SysTick_Type</a></li>
<li>CALR&#160;:&#160;<a class="el" href="struct_r_t_c___type_def.html#aea66ea813830c2f3ff207464794397a4">RTC_TypeDef</a></li>
<li>CBNDTR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#ad27a6cee3f90bb9221cc993a6d4c10c3">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___link_node_type_def.html#a37e670bfdad02877eb8291fbc43f0a21">MDMA_LinkNodeTypeDef</a></li>
<li>CBRUR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#a94503b7dc3f8d03923ecf4376b5956a9">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___link_node_type_def.html#a2123db2d7b0990b1b370df6b0f4a00a4">MDMA_LinkNodeTypeDef</a></li>
<li>CCCR&#160;:&#160;<a class="el" href="struct_f_d_c_a_n___global_type_def.html#a52cdc2ea561e6195e42f131707140184">FDCAN_GlobalTypeDef</a>, <a class="el" href="struct_s_y_s_c_f_g___type_def.html#a916b26f435ff938144e0e74d1e4b68b3">SYSCFG_TypeDef</a></li>
<li>CCCSR&#160;:&#160;<a class="el" href="struct_s_y_s_c_f_g___type_def.html#a4b72e8104e124ffe7da8f6b1e42ff1e5">SYSCFG_TypeDef</a></li>
<li>CCER&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">TIM_TypeDef</a></li>
<li>CCFG&#160;:&#160;<a class="el" href="struct_f_d_c_a_n___clock_calibration_unit___type_def.html#ac0f99874e288f8e874bc8c6f04383d11">FDCAN_ClockCalibrationUnit_TypeDef</a></li>
<li>CCMR1&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">TIM_TypeDef</a></li>
<li>CCMR2&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#aa8129ca70a2232c91c8cfcaf375249f6">TIM_TypeDef</a></li>
<li>CCMR3&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#ac0dcd8f9118b07b16cd79d03cb1a0904">TIM_TypeDef</a></li>
<li>CCR&#160;:&#160;<a class="el" href="struct_a_d_c___common___type_def.html#aee6d4af7571a1bad2fec9e7b53733277">ADC_Common_TypeDef</a>, <a class="el" href="struct_b_d_m_a___channel___type_def.html#ae64e6fa9795e9cf60e93988c9da1a97b">BDMA_Channel_TypeDef</a>, <a class="el" href="struct_d_a_c___type_def.html#a9394949a84c836614c6010809e8fe52f">DAC_TypeDef</a>, <a class="el" href="struct_d_m_a_m_u_x___channel___type_def.html#ac780e241416beffb638e61756049fffc">DMAMUX_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___channel___type_def.html#a835c47def48257f36879ad0ff5e3bb8e">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_o_c_t_o_s_p_i___type_def.html#a3fa9d712bb263f5e5138df69b2e3bd00">OCTOSPI_TypeDef</a>, <a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga2d6653b0b70faac936046a02809b577f">SCB_Type</a>, <a class="el" href="struct_v_r_e_f_b_u_f___type_def.html#a40b3026dad2b763980f552821c21a998">VREFBUF_TypeDef</a></li>
<li>CCR1&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___type_def.html#a1616234c768f3942a208890a61b8489a">FLASH_TypeDef</a>, <a class="el" href="struct_t_i_m___type_def.html#a0dd9c06729a5eb6179c6d0d60faca7ed">TIM_TypeDef</a></li>
<li>CCR2&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#a4d1171e9a61538424b8ef1f2571986d0">TIM_TypeDef</a></li>
<li>CCR3&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#ac83441bfb8d0287080dcbd945a272a74">TIM_TypeDef</a></li>
<li>CCR4&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#a5ba381c3f312fdf5e0b4119641b3b0aa">TIM_TypeDef</a></li>
<li>CCR5&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#af30dc563e6c1b7b7e01e393feb484080">TIM_TypeDef</a></li>
<li>CCR6&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#a374f851b5f1097a3ebd3f494ded6512a">TIM_TypeDef</a></li>
<li>CCSIDR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gafd063c9297a1a3b67e6d1d5e179e6a0e">SCB_Type</a></li>
<li>CCVR&#160;:&#160;<a class="el" href="struct_s_y_s_c_f_g___type_def.html#a4e4ef9c45d95b95d5ea7fa166ed6c88c">SYSCFG_TypeDef</a></li>
<li>CDAR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#aa79c99d83c06c265c094b0e2bb462993">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___link_node_type_def.html#a13591689c3d723959969ce6a36e46eec">MDMA_LinkNodeTypeDef</a></li>
<li>CDR&#160;:&#160;<a class="el" href="struct_a_d_c___common___type_def.html#a6f7399bf70f677ef5de46a3038f414e1">ADC_Common_TypeDef</a></li>
<li>CDR2&#160;:&#160;<a class="el" href="struct_a_d_c___common___type_def.html#a8ee71d207d53fc1cfb5e45acb59e181e">ADC_Common_TypeDef</a></li>
<li>CDSR&#160;:&#160;<a class="el" href="struct_l_t_d_c___type_def.html#a6d6675f23322e241122468935ee60ed1">LTDC_TypeDef</a></li>
<li>CecClockSelection&#160;:&#160;<a class="el" href="struct_r_c_c___periph_c_l_k_init_type_def.html#a344e2489c3faf2150fafbafc86b86812">RCC_PeriphCLKInitTypeDef</a></li>
<li>CESR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#a9811369e1b621b63eff14f3a50986062">MDMA_Channel_TypeDef</a></li>
<li>CFBAR&#160;:&#160;<a class="el" href="struct_l_t_d_c___layer___type_def.html#aa79c0c2be9b6f8e4f034d8d5fe8e9345">LTDC_Layer_TypeDef</a></li>
<li>CFBLNR&#160;:&#160;<a class="el" href="struct_l_t_d_c___layer___type_def.html#adbd3ad2a70d1578d630acfdb9a526320">LTDC_Layer_TypeDef</a></li>
<li>CFBLR&#160;:&#160;<a class="el" href="struct_l_t_d_c___layer___type_def.html#ae4673c5b4a2df7b770d82e43b1806ccf">LTDC_Layer_TypeDef</a></li>
<li>CFG1&#160;:&#160;<a class="el" href="struct_s_p_i___type_def.html#a1fd1ba3ba655258308d26cdcfaf4bc5e">SPI_TypeDef</a></li>
<li>CFG2&#160;:&#160;<a class="el" href="struct_s_p_i___type_def.html#ab40edb77993e6f1343c5999f62e5a157">SPI_TypeDef</a></li>
<li>CFGR&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#a40a83116e2176d7197fc4b7d0eb08609">ADC_TypeDef</a>, <a class="el" href="struct_c_e_c___type_def.html#a91a55cd277c20e5c5ad228fd9013d014">CEC_TypeDef</a>, <a class="el" href="struct_c_o_m_p___common___type_def.html#ab153c36dc76dc3a8ead137e0026654f9">COMP_Common_TypeDef</a>, <a class="el" href="struct_c_o_m_p___type_def.html#ab37072133905386c40aca88dc5ea7339">COMP_TypeDef</a>, <a class="el" href="struct_c_r_s___type_def.html#ad51dab454cab135414e565504d776a30">CRS_TypeDef</a>, <a class="el" href="struct_d_l_y_b___type_def.html#a8429c65c78d2861923cd29025603c5a7">DLYB_TypeDef</a>, <a class="el" href="struct_l_p_t_i_m___type_def.html#a35c555cdc39e12f291f1e96bdf953ec4">LPTIM_TypeDef</a>, <a class="el" href="struct_r_c_c___type_def.html#a0721b1b729c313211126709559fad371">RCC_TypeDef</a>, <a class="el" href="struct_s_y_s_c_f_g___type_def.html#af9e58364169ac3d84d12f9e4aabf1f62">SYSCFG_TypeDef</a></li>
<li>CFGR1&#160;:&#160;<a class="el" href="struct_d_t_s___type_def.html#a6aebcef8920afb0193765f3fa74a2357">DTS_TypeDef</a></li>
<li>CFGR2&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#a0a4c0d337b0e546e549678b77ea63246">ADC_TypeDef</a>, <a class="el" href="struct_l_p_t_i_m___type_def.html#a71583a9ce4c19ca3b4f7f1e7f7b7b662">LPTIM_TypeDef</a></li>
<li>CFR&#160;:&#160;<a class="el" href="struct_d_m_a_m_u_x___channel_status___type_def.html#acafeb4de92a6d63af5cfb33057555ee0">DMAMUX_ChannelStatus_TypeDef</a>, <a class="el" href="struct_w_w_d_g___type_def.html#adcd6a7e5d75022e46ce60291f4b8544c">WWDG_TypeDef</a></li>
<li>CFSR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga0cda9e061b42373383418663092ad19a">SCB_Type</a></li>
<li>Channel&#160;:&#160;<a class="el" href="struct_t_i_m___handle_type_def.html#ae9c5a11c1f5b27c808c0aca453e63870">TIM_HandleTypeDef</a></li>
<li>ChannelNState&#160;:&#160;<a class="el" href="struct_t_i_m___handle_type_def.html#ac7648b2c1fd8d3fb38913fbad5379b11">TIM_HandleTypeDef</a></li>
<li>ChannelState&#160;:&#160;<a class="el" href="struct_t_i_m___handle_type_def.html#a97dfe939e85a354c2dd8c66bef48e5a2">TIM_HandleTypeDef</a></li>
<li>CHAWSCDR&#160;:&#160;<a class="el" href="struct_d_f_s_d_m___channel___type_def.html#a418e04c7b9a06d216ec9af9d040f34bb">DFSDM_Channel_TypeDef</a></li>
<li>CHCFGR1&#160;:&#160;<a class="el" href="struct_d_f_s_d_m___channel___type_def.html#ad59d0c9e6a23c073d5074c1080437509">DFSDM_Channel_TypeDef</a></li>
<li>CHCFGR2&#160;:&#160;<a class="el" href="struct_d_f_s_d_m___channel___type_def.html#a06ccb02a66ad9b39d5df801ffccdc0bb">DFSDM_Channel_TypeDef</a></li>
<li>CHDATINR&#160;:&#160;<a class="el" href="struct_d_f_s_d_m___channel___type_def.html#a82d9028493b845db2391dfbec944bf2e">DFSDM_Channel_TypeDef</a></li>
<li>CHWDATAR&#160;:&#160;<a class="el" href="struct_d_f_s_d_m___channel___type_def.html#a662b02dfee03cfde7809fd168626f87f">DFSDM_Channel_TypeDef</a></li>
<li>CICR&#160;:&#160;<a class="el" href="struct_r_c_c___type_def.html#a28e7b1071afa5b6c98f8050890159b05">RCC_TypeDef</a></li>
<li>CID&#160;:&#160;<a class="el" href="struct_u_s_b___o_t_g___global_type_def.html#a5c67046606b7e64fb03c4ac550156156">USB_OTG_GlobalTypeDef</a></li>
<li>CID0&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga30bb2b166b1723867da4a708935677ba">ITM_Type</a></li>
<li>CID1&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gac40df2c3a6cef02f90b4e82c8204756f">ITM_Type</a></li>
<li>CID2&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga8000b92e4e528ae7ac4cb8b8d9f6757d">ITM_Type</a></li>
<li>CID3&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga43451f43f514108d9eaed5b017f8d921">ITM_Type</a></li>
<li>CIDR0&#160;:&#160;<a class="el" href="struct_d_b_g_m_c_u___type_def.html#a4251fb34556fa52aaded20acdfa3c09e">DBGMCU_TypeDef</a></li>
<li>CIDR1&#160;:&#160;<a class="el" href="struct_d_b_g_m_c_u___type_def.html#a929f2d4e6fa1f7d8acf7a85f60d729aa">DBGMCU_TypeDef</a></li>
<li>CIDR2&#160;:&#160;<a class="el" href="struct_d_b_g_m_c_u___type_def.html#a899def83ae7e50fd889b0ff3a7200b87">DBGMCU_TypeDef</a></li>
<li>CIDR3&#160;:&#160;<a class="el" href="struct_d_b_g_m_c_u___type_def.html#aa0c05391c70942f7b6d70d9a7669fff1">DBGMCU_TypeDef</a></li>
<li>CIER&#160;:&#160;<a class="el" href="struct_r_c_c___type_def.html#a6d0c293e1198ffec4802a19328ba73bb">RCC_TypeDef</a></li>
<li>CIFCR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#a33065aa1d54e1aba74570382f7e367d4">MDMA_Channel_TypeDef</a></li>
<li>CIFR&#160;:&#160;<a class="el" href="struct_r_c_c___type_def.html#afee6ba7ba2583577492d14f08a1a5e74">RCC_TypeDef</a></li>
<li>CISR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#a5a5efbf83f104427b927e6b207cf26d1">MDMA_Channel_TypeDef</a></li>
<li>CKCR&#160;:&#160;<a class="el" href="struct_l_t_d_c___layer___type_def.html#a1037f0255519c1c6c14af5b17a4de3ca">LTDC_Layer_TypeDef</a></li>
<li>CkperClockSelection&#160;:&#160;<a class="el" href="struct_r_c_c___periph_c_l_k_init_type_def.html#a2847c5846fbf04e83aae71ef5bef1c78">RCC_PeriphCLKInitTypeDef</a></li>
<li>CLAIMCLR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga0e10e292cb019a832b03ddd055b2f6ac">TPI_Type</a></li>
<li>CLAIMSET&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gaf8b7d15fa5252b733dd4b11fa1b5730a">TPI_Type</a></li>
<li>CLAR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#a5b6aba31216cd09145878456e935262d">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___link_node_type_def.html#a30d688477fb95aa2826a64004017698c">MDMA_LinkNodeTypeDef</a></li>
<li>classes&#160;:&#160;<a class="el" href="structarm__svm__linear__instance__f32.html#a8b881b1d0beb2fdc0087b520bedaeb05">arm_svm_linear_instance_f32</a>, <a class="el" href="structarm__svm__polynomial__instance__f32.html#adcff163beaf39f48f6059402a58002b4">arm_svm_polynomial_instance_f32</a>, <a class="el" href="structarm__svm__rbf__instance__f32.html#a54056ecd4e713c7612e291d32906fb65">arm_svm_rbf_instance_f32</a>, <a class="el" href="structarm__svm__sigmoid__instance__f32.html#a631904ac7c15e35dc9d8342af33970a1">arm_svm_sigmoid_instance_f32</a></li>
<li>classPriors&#160;:&#160;<a class="el" href="structarm__gaussian__naive__bayes__instance__f32.html#a5eb3e56b09bc80fc2d169cdd7c0c425f">arm_gaussian_naive_bayes_instance_f32</a></li>
<li>ClearInputFilter&#160;:&#160;<a class="el" href="struct_t_i_m___clear_input_config_type_def.html#a6d2e06a970e30aaf4f8a6091e443eecf">TIM_ClearInputConfigTypeDef</a></li>
<li>ClearInputPolarity&#160;:&#160;<a class="el" href="struct_t_i_m___clear_input_config_type_def.html#a49dbc65edc5316822fcabd61cc8409de">TIM_ClearInputConfigTypeDef</a></li>
<li>ClearInputPrescaler&#160;:&#160;<a class="el" href="struct_t_i_m___clear_input_config_type_def.html#a509cecb64fec71391ddc8b4703e09cfe">TIM_ClearInputConfigTypeDef</a></li>
<li>ClearInputSource&#160;:&#160;<a class="el" href="struct_t_i_m___clear_input_config_type_def.html#a776d2f14021a82e022468fd46594b8a0">TIM_ClearInputConfigTypeDef</a></li>
<li>ClearInputState&#160;:&#160;<a class="el" href="struct_t_i_m___clear_input_config_type_def.html#a01d4b91dd297c4f0582a4d9179abf32f">TIM_ClearInputConfigTypeDef</a></li>
<li>CLIDR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gad9899f5775251cf5ef0cb0845527afc2">SCB_Type</a></li>
<li>CLKCR&#160;:&#160;<a class="el" href="struct_s_d_m_m_c___type_def.html#ac432d7f247e2f199f387a9d81a70dbe3">SDMMC_TypeDef</a></li>
<li>CLKPhase&#160;:&#160;<a class="el" href="struct_s_p_i___init_type_def.html#ab21a458209f2588f49a2353c56f62625">SPI_InitTypeDef</a></li>
<li>CLKPolarity&#160;:&#160;<a class="el" href="struct_s_p_i___init_type_def.html#a96922c7ff9e589ebd9611fc4ab730454">SPI_InitTypeDef</a></li>
<li>ClockDivision&#160;:&#160;<a class="el" href="struct_t_i_m___base___init_type_def.html#ade59c3a547a5409da845592f30596d17">TIM_Base_InitTypeDef</a></li>
<li>ClockFilter&#160;:&#160;<a class="el" href="struct_t_i_m___clock_config_type_def.html#adaf66568c766f75c4c661a872ca399e3">TIM_ClockConfigTypeDef</a></li>
<li>ClockPolarity&#160;:&#160;<a class="el" href="struct_t_i_m___clock_config_type_def.html#a66453fa8dc8a300267ff5aba08eff5c4">TIM_ClockConfigTypeDef</a></li>
<li>ClockPrescaler&#160;:&#160;<a class="el" href="struct_t_i_m___clock_config_type_def.html#ae4c0cb6f58da0ec7b99f1c6411d2fee1">TIM_ClockConfigTypeDef</a>, <a class="el" href="struct_u_a_r_t___init_type_def.html#af611d87f44dd63f0719f202f92c90df3">UART_InitTypeDef</a></li>
<li>ClockSource&#160;:&#160;<a class="el" href="struct_t_i_m___clock_config_type_def.html#a54c329013b5f6f87d1c3d2495fca84d2">TIM_ClockConfigTypeDef</a></li>
<li>ClockType&#160;:&#160;<a class="el" href="struct_r_c_c___clk_init_type_def.html#a93a53676a1cfc5b55b8b990e7ff4dac5">RCC_ClkInitTypeDef</a></li>
<li>CLRFR&#160;:&#160;<a class="el" href="struct_s_a_i___block___type_def.html#a52dffdfbe572129cc142023f3daeeffe">SAI_Block_TypeDef</a></li>
<li>CLUTWR&#160;:&#160;<a class="el" href="struct_l_t_d_c___layer___type_def.html#ae4ce84d11912847542fcdc03ae337176">LTDC_Layer_TypeDef</a></li>
<li>CM0AR&#160;:&#160;<a class="el" href="struct_b_d_m_a___channel___type_def.html#a99ef9f96e0a3766cdd15bc943425d06d">BDMA_Channel_TypeDef</a></li>
<li>CM1AR&#160;:&#160;<a class="el" href="struct_b_d_m_a___channel___type_def.html#a9f1d5c8334a5fdc0f71d886ff4d5e2ec">BDMA_Channel_TypeDef</a></li>
<li>CMAR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#a78006e734147831c891244e439493d8f">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___link_node_type_def.html#a58d01493f0832beac3fa2a8d316287da">MDMA_LinkNodeTypeDef</a></li>
<li>CMD&#160;:&#160;<a class="el" href="struct_s_d_m_m_c___type_def.html#ad67342999b4fb5e7c7249935ea96d02f">SDMMC_TypeDef</a></li>
<li>CMDR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#acbc1a147afb2fd72925a88697447993c">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___link_node_type_def.html#a35f2f998391ce5133f6e1f4ca3e9a21c">MDMA_LinkNodeTypeDef</a></li>
<li>CMP&#160;:&#160;<a class="el" href="struct_l_p_t_i_m___type_def.html#a0f22edd659052ecb52c692e507a8ebdc">LPTIM_TypeDef</a></li>
<li>CNDTR&#160;:&#160;<a class="el" href="struct_b_d_m_a___channel___type_def.html#a8b3eaea3e3ab6a598d1202f48b706154">BDMA_Channel_TypeDef</a></li>
<li>CNT&#160;:&#160;<a class="el" href="struct_l_p_t_i_m___type_def.html#a8c510cd4e483030373cb03eb347d65df">LPTIM_TypeDef</a>, <a class="el" href="struct_t_i_m___type_def.html#a6fdd2a7fb88d28670b472aaac0d9d262">TIM_TypeDef</a></li>
<li>coef0&#160;:&#160;<a class="el" href="structarm__svm__polynomial__instance__f32.html#a2acd6714eb19d98f72badd98009c85aa">arm_svm_polynomial_instance_f32</a>, <a class="el" href="structarm__svm__sigmoid__instance__f32.html#af13f045fdeedabdf7671b8625507b92d">arm_svm_sigmoid_instance_f32</a></li>
<li>coeffs&#160;:&#160;<a class="el" href="structarm__spline__instance__f32.html#a2c2f708ce9ae0393000daa86c101181d">arm_spline_instance_f32</a></li>
<li>Commutation_Delay&#160;:&#160;<a class="el" href="struct_t_i_m___hall_sensor___init_type_def.html#a822efefca8a13af284e84070bd19bb91">TIM_HallSensor_InitTypeDef</a></li>
<li>COMP0&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga61c2965af5bc0643f9af65620b0e67c9">DWT_Type</a></li>
<li>COMP1&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga38714af6b7fa7c64d68f5e1efbe7a931">DWT_Type</a></li>
<li>COMP10&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gacf26842434e5cd1487a49812ec842d03">DWT_Type</a></li>
<li>COMP11&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gaa199b91c854edd21ded38b8922d1e2a7">DWT_Type</a></li>
<li>COMP12&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga9115fd187d8cbcb9d6ec5eba938b81ea">DWT_Type</a></li>
<li>COMP13&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gabc29ac14df61ec3f8f3d28ca92892d8a">DWT_Type</a></li>
<li>COMP14&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga85368a4ec78f4074e5f9cbba92ae1eb9">DWT_Type</a></li>
<li>COMP15&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gaa46b44e5aacd3ca3937741f423ab480f">DWT_Type</a></li>
<li>COMP2&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga5ae6dde39989f27bae90afc2347deb46">DWT_Type</a></li>
<li>COMP3&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga85eb73d1848ac3f82d39d6c3e8910847">DWT_Type</a></li>
<li>COMP4&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga86bc7f4ad425a05b29978a6f97563783">DWT_Type</a></li>
<li>COMP5&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga07667ec9dd833ecab52bf2cf802d9acb">DWT_Type</a></li>
<li>COMP6&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga1256ac92acb94add255ff31aca31070d">DWT_Type</a></li>
<li>COMP7&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga46db6f5289d840f0b9886ae598352452">DWT_Type</a></li>
<li>COMP8&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gaee138bc70746585e4ccf62557954c07f">DWT_Type</a></li>
<li>COMP9&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gabf79b853fc2d25de9c03bdb183e4aee0">DWT_Type</a></li>
<li>CounterMode&#160;:&#160;<a class="el" href="struct_t_i_m___base___init_type_def.html#a16d0c02a8f35426360a64c0706656e35">TIM_Base_InitTypeDef</a></li>
<li>CPACR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gac6a860c1b8d8154a1f00d99d23b67764">SCB_Type</a></li>
<li>CPAR&#160;:&#160;<a class="el" href="struct_b_d_m_a___channel___type_def.html#a191a5e7c35694cc5c8f1e01a8aa4ea60">BDMA_Channel_TypeDef</a></li>
<li>CPICNT&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga2c08096c82abe245c0fa97badc458154">DWT_Type</a></li>
<li>CPPWR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga356efebfcbdaecaf1176e6cd86a60bf1">SCnSCB_Type</a></li>
<li>CPSR&#160;:&#160;<a class="el" href="struct_l_t_d_c___type_def.html#af019d85ce2b876ee99d994a09de12ec3">LTDC_TypeDef</a></li>
<li>CPUCR&#160;:&#160;<a class="el" href="struct_p_w_r___type_def.html#accb03e795c571cf5db2c3827ab7329b4">PWR_TypeDef</a></li>
<li>CPUID&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga21e08d546d8b641bee298a459ea73e46">SCB_Type</a></li>
<li>CR&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#a6126350919b341bfb13c0b24b30dc22a">ADC_TypeDef</a>, <a class="el" href="struct_c_e_c___type_def.html#ab272f34d3acb1edeaaeaf087b284d77f">CEC_TypeDef</a>, <a class="el" href="struct_c_r_c___type_def.html#af33fa5c173e1c102e6d0242fe60e569f">CRC_TypeDef</a>, <a class="el" href="struct_c_r_s___type_def.html#a8f1000451ee16f2da1ba6cc3411dd36a">CRS_TypeDef</a>, <a class="el" href="struct_d_a_c___type_def.html#a394324f0b573837ca15a87127b2a37ea">DAC_TypeDef</a>, <a class="el" href="struct_d_b_g_m_c_u___type_def.html#a15981828f2b915d38570cf6684e99a53">DBGMCU_TypeDef</a>, <a class="el" href="struct_d_c_m_i___type_def.html#a3cfcc9860ca551cbcb10c1c3dd4304f0">DCMI_TypeDef</a>, <a class="el" href="struct_d_l_y_b___type_def.html#a3375fa4f55a9be87b27cd2c5f45b892e">DLYB_TypeDef</a>, <a class="el" href="struct_d_m_a2_d___type_def.html#afb0ef686f69afae3e9614a9b30558dcf">DMA2D_TypeDef</a>, <a class="el" href="struct_d_m_a___stream___type_def.html#af893adc5e821b15d813237b2bfe4378b">DMA_Stream_TypeDef</a>, <a class="el" href="struct_f_m_a_c___type_def.html#afe75a3c4c2d474f995660f69e8885075">FMAC_TypeDef</a>, <a class="el" href="struct_h_s_e_m___type_def.html#ab207840b89471c745e4302e2970fed13">HSEM_TypeDef</a>, <a class="el" href="struct_l_p_t_i_m___type_def.html#aa4900090e51a693ed07d4a90eb45ddf8">LPTIM_TypeDef</a>, <a class="el" href="struct_l_t_d_c___layer___type_def.html#a3f9827b30a402fd3d85fe4f4b8eb49c9">LTDC_Layer_TypeDef</a>, <a class="el" href="struct_o_c_t_o_s_p_i___type_def.html#ac71d27abd195793719c5a5991191e8a4">OCTOSPI_TypeDef</a>, <a class="el" href="struct_o_c_t_o_s_p_i_m___type_def.html#a00583bb77d8e87de7ad6ce630876e45c">OCTOSPIM_TypeDef</a>, <a class="el" href="struct_p_s_s_i___type_def.html#ae0c882dfbd354da63f59e9e42bfe3877">PSSI_TypeDef</a>, <a class="el" href="struct_r_a_m_e_c_c___monitor_type_def.html#a60e78c3b36e9c3d77c9448326a70b291">RAMECC_MonitorTypeDef</a>, <a class="el" href="struct_r_c_c___type_def.html#abcb9ff48b9afb990283fefad0554b5b3">RCC_TypeDef</a>, <a class="el" href="struct_r_n_g___type_def.html#ab422a7aeea33d29d0f8b841bb461e3a8">RNG_TypeDef</a>, <a class="el" href="struct_r_t_c___type_def.html#a731d9209ce40dce6ea61fcc6f818c892">RTC_TypeDef</a>, <a class="el" href="struct_s_p_d_i_f_r_x___type_def.html#af97c3ae3a1ced6864b75ee530d96e2d7">SPDIFRX_TypeDef</a>, <a class="el" href="struct_s_w_p_m_i___type_def.html#aecc2dc56573d57f5f476c380892ea2e2">SWPMI_TypeDef</a>, <a class="el" href="struct_w_w_d_g___type_def.html#a4caf530d45f7428c9700d9c0057135f8">WWDG_TypeDef</a></li>
<li>CR1&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___type_def.html#a26d5b300bc241e18ae7ab136215985fc">FLASH_TypeDef</a>, <a class="el" href="struct_i2_c___type_def.html#a91782f7b81475b0e3c3779273abd26aa">I2C_TypeDef</a>, <a class="el" href="struct_p_w_r___type_def.html#a50f96f92968bc5b9b40b870531dde182">PWR_TypeDef</a>, <a class="el" href="struct_s_a_i___block___type_def.html#a8935f3f22c733c1cb5a05cecf3cfa38c">SAI_Block_TypeDef</a>, <a class="el" href="struct_s_p_i___type_def.html#a6ecd5cb63b85c381bd67dc90dd4f573a">SPI_TypeDef</a>, <a class="el" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">TIM_TypeDef</a>, <a class="el" href="struct_u_s_a_r_t___type_def.html#a6d7dcd3972a162627bc3470cbf992ec4">USART_TypeDef</a></li>
<li>CR2&#160;:&#160;<a class="el" href="struct_i2_c___type_def.html#a29eb47db03d5ad7e9b399f8895f1768c">I2C_TypeDef</a>, <a class="el" href="struct_p_w_r___type_def.html#a8426bae04fc4cae7425f07c50f2359ec">PWR_TypeDef</a>, <a class="el" href="struct_s_a_i___block___type_def.html#ad9976416e6199c8c1f7bcdabe20e4bd2">SAI_Block_TypeDef</a>, <a class="el" href="struct_s_p_i___type_def.html#a38cb89a872e456e6ecd29b6c71d85600">SPI_TypeDef</a>, <a class="el" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">TIM_TypeDef</a>, <a class="el" href="struct_u_s_a_r_t___type_def.html#aa7ede2de6204c3fc4bd9fb328801c99a">USART_TypeDef</a></li>
<li>CR3&#160;:&#160;<a class="el" href="struct_p_w_r___type_def.html#a5b7c92606919491fb50de53447078fd4">PWR_TypeDef</a>, <a class="el" href="struct_u_s_a_r_t___type_def.html#af2991da9a4e1539530cd6b7b327199cc">USART_TypeDef</a></li>
<li>CRCCalculation&#160;:&#160;<a class="el" href="struct_s_p_i___init_type_def.html#a3472de9bd9247c1d97312aff7e58e385">SPI_InitTypeDef</a></li>
<li>CRCCR1&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___type_def.html#a4fd52b83f3cacc9f208ecf5804a6e886">FLASH_TypeDef</a></li>
<li>CRCDATA&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___type_def.html#a9c40b24687d5ac91a17c622a9248aac5">FLASH_TypeDef</a></li>
<li>CRCEADD1&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___type_def.html#a213623a15e76ba66797fb6258dbe6d38">FLASH_TypeDef</a></li>
<li>CRCEndAddr&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___c_r_c_init_type_def.html#af0051ec432927719c91b33a9f7184fe3">FLASH_CRCInitTypeDef</a></li>
<li>CRCLength&#160;:&#160;<a class="el" href="struct_s_p_i___init_type_def.html#ade3815f539adcdeba866ab26a5f59c99">SPI_InitTypeDef</a></li>
<li>CRCPOLY&#160;:&#160;<a class="el" href="struct_s_p_i___type_def.html#a03d6f39b695fb8e316e97c8a089cd46b">SPI_TypeDef</a></li>
<li>CRCPolynomial&#160;:&#160;<a class="el" href="struct_s_p_i___init_type_def.html#abdaf3ccbfa4ef68cc81fd32f29baa678">SPI_InitTypeDef</a></li>
<li>CRCSADD1&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___type_def.html#a97ffd6724257a7f89e9b0802d704fc1e">FLASH_TypeDef</a></li>
<li>CRCSize&#160;:&#160;<a class="el" href="struct_____s_p_i___handle_type_def.html#abef898bf323d7e9d693665f12b6f6239">__SPI_HandleTypeDef</a></li>
<li>CRCStartAddr&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___c_r_c_init_type_def.html#a4a85047d945aa22901847e85b2ae3778">FLASH_CRCInitTypeDef</a></li>
<li>CREL&#160;:&#160;<a class="el" href="struct_f_d_c_a_n___clock_calibration_unit___type_def.html#a021f11746827889db4d06624fb64b014">FDCAN_ClockCalibrationUnit_TypeDef</a>, <a class="el" href="struct_f_d_c_a_n___global_type_def.html#ac6cd9a2f83d747130d137d6374f4f042">FDCAN_GlobalTypeDef</a></li>
<li>CRRCR&#160;:&#160;<a class="el" href="struct_r_c_c___type_def.html#a1694a01e1a23db1694288fb3a86e9f18">RCC_TypeDef</a></li>
<li>CSAR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#a9b845a89d1c4dec3e6df2d443955c0d8">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___link_node_type_def.html#ab09f27518c5b847b2710c8289d4ed662">MDMA_LinkNodeTypeDef</a></li>
<li>CSICalibrationValue&#160;:&#160;<a class="el" href="struct_r_c_c___osc_init_type_def.html#ae4b53b39a73462d9194323304f22952d">RCC_OscInitTypeDef</a></li>
<li>CSICFGR&#160;:&#160;<a class="el" href="struct_r_c_c___type_def.html#aa2d7bfc4c20fea2c980bda5114e31384">RCC_TypeDef</a></li>
<li>CSIState&#160;:&#160;<a class="el" href="struct_r_c_c___osc_init_type_def.html#ac78f1dc9bea6e0f83e1ca8719a6e688f">RCC_OscInitTypeDef</a></li>
<li>CSPSR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga8826aa84e5806053395a742d38d59d0f">TPI_Type</a></li>
<li>CSR&#160;:&#160;<a class="el" href="struct_a_d_c___common___type_def.html#ac38e24f600f9e134a54a0c43b976a4f4">ADC_Common_TypeDef</a>, <a class="el" href="struct_c_o_r_d_i_c___type_def.html#a60112828255218fbee25d903849dee11">CORDIC_TypeDef</a>, <a class="el" href="struct_d_m_a_m_u_x___channel_status___type_def.html#a2b806557d4176378c888423e1d4bdecc">DMAMUX_ChannelStatus_TypeDef</a>, <a class="el" href="struct_o_p_a_m_p___type_def.html#aa3123f8a6ca8605b6687b9ee3f11e8ef">OPAMP_TypeDef</a>, <a class="el" href="struct_r_c_c___type_def.html#a7e913b8bf59d4351e1f3d19387bd05b9">RCC_TypeDef</a>, <a class="el" href="struct_s_p_d_i_f_r_x___type_def.html#a8d811e4f5a16f36d6cb45d1369eec51b">SPDIFRX_TypeDef</a>, <a class="el" href="struct_v_r_e_f_b_u_f___type_def.html#acd109d8fd241a08ab359a57cb0250fd9">VREFBUF_TypeDef</a></li>
<li>CSR1&#160;:&#160;<a class="el" href="struct_p_w_r___type_def.html#a682b6c3f4af70d7faf280b2e65b3d4a4">PWR_TypeDef</a></li>
<li>CSSELR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gad3884e8b6504ec63c1eaa8742e94df3d">SCB_Type</a></li>
<li>CSTAT&#160;:&#160;<a class="el" href="struct_f_d_c_a_n___clock_calibration_unit___type_def.html#afba765bf8f1f8cd8a985ed2599f7c6a9">FDCAN_ClockCalibrationUnit_TypeDef</a></li>
<li>CTBR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#a68b30850de97b936637d53508be9fdf2">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___link_node_type_def.html#aa3ce729f2ab00cabbd8a673f729ef38e">MDMA_LinkNodeTypeDef</a></li>
<li>CTCR&#160;:&#160;<a class="el" href="struct_m_d_m_a___channel___type_def.html#a17b5ca2bff81a3b7ffffd4b3471973ae">MDMA_Channel_TypeDef</a>, <a class="el" href="struct_m_d_m_a___link_node_type_def.html#a1aba49c45628919345b11378869cccd2">MDMA_LinkNodeTypeDef</a></li>
<li>CTR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gaf3fe705fef8762763b6d61dbdf0ccc3d">SCB_Type</a></li>
<li>CTRL&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gadd790c53410023b3b581919bb681fe2a">DWT_Type</a>, <a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga4d81d6aa73a9287bafba2bcc5ffc6d18">MPU_Type</a>, <a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga875e7afa5c4fd43997fb544a4ac6e37e">SysTick_Type</a></li>
<li>CWD&#160;:&#160;<a class="el" href="struct_f_d_c_a_n___clock_calibration_unit___type_def.html#abdcb38854d7681894986242209b13b19">FDCAN_ClockCalibrationUnit_TypeDef</a></li>
<li>CWSIZER&#160;:&#160;<a class="el" href="struct_d_c_m_i___type_def.html#a1b9c8048339e19b110ecfbea486f55df">DCMI_TypeDef</a></li>
<li>CWSTRTR&#160;:&#160;<a class="el" href="struct_d_c_m_i___type_def.html#a4d58830323e567117c12ae3feac613b9">DCMI_TypeDef</a></li>
<li>CYCCNT&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga102eaa529d9098242851cb57c52b42d9">DWT_Type</a></li>
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